Japanese Laid-Open Patent Publication No. 2001-68993 describes an example of a semiconductor device including a programmable logic circuit. The logic circuit includes a plurality of calculation units and couples the calculation units in accordance with configuration information supplied from a control circuit (e.g., CPU) provided in the semiconductor device. When a logic structure corresponding to the configuration information is configured in the logic circuit, the logic circuit outputs a completion flag. The control circuit responds to the completion flag and instructs the logic circuit to perform calculation. Then, the logic circuit performs the processing based on the instruction and outputs a completion flag upon completion of the processing. In response to the completion flag, the control circuit sets the subsequent configuration information in the logic circuit. In such a manner, the subsequent configuration information is set every time the logic circuit completes the processing.
The control circuit sets configuration information in response to a completion flag indicating the completion of processing in the logic circuit. Thus, when the programmable logic circuit performs a plurality of processes, the subsequent configuration information is not set in each logic circuit until all of the processes are completed. The delay in setting the configuration information in each logic circuit may lead to an increase in processing time.